The present invention is related to systems and methods for detecting and decoding digital information. More particularly, the present invention relates to systems and methods for detecting and correcting errors associated with an information transfer.
Digital communication systems (e.g., sets of wireless communication devices) and digital storage systems (e.g., hard disk drives) provide for transfer of different types of information. For example, in the case of communication systems, digital information is transferred substantially in real time from one communication device to another. In contrast, digital information transfer involving digital storage systems typically involves non-real time transfer of digital information that was previously stored to a storage device. While there are fundamental differences between the aforementioned information transfer approaches, the general goal of both approaches is to transfer information as accurately as possible in the presence of impairments such as noise and inter-symbol interference (ISI).
The goal of increasing accuracy of information transfer has fueled development of progressively more complex information transfer approaches that include increasingly elaborate error correction schemes (ECSs). As an example, a state of the art information transfer approach may include a substantial number of parity bits built into the information being transferred. These parity bits introduce redundancy into the signal prior to transmission, and are subsequently used to decode the encoded information. FIG. 1 depicts an exemplary state of the art transfer system tailored for a digital storage system. It should be noted that a typical state of the art system tailored for a digital communication system would include the same level of complexity or possibly greater.
Turning to FIG. 1, a block diagram is provided for a known digital storage system 1 that utilizes a parity checking approach for error detection and correction. Digital storage system 1 includes an encoder 2 that encodes information by including parity bits in the information. Encoder 2 is typically a parity based block code encoder. After the original information is encoded, it is provided to recording channel 3 that typically includes various physical and electrical components, such as a read write head, a read write head armature, a recoding media, a pre-amplifier, or other related circuitry or components.
The encoded information is passed from recording channel 3 to a soft output Viterbi algorithm (SOVA) channel detector 4. SOVA channel detector 4 processes the received encoded information using a bit detection algorithm. The output of SOVA channel detector 4 includes a combination of hard decisions and reliability estimates (i.e., respective estimates as to the reliability of the respective hard decisions). Both the soft and hard outputs of SOVA channel detector 4 are provided to a decoder 5 that is responsible for decoding the recovered information bits using the parity bits.
Operation of digital storage system 1 is exemplified where original information (e.g., uk=010110) is to be stored in recording channel 3. The original information is represented by Table 1 below.
TABLE 1Original Information (uk)011100
The original information (uk) is provided to encoder 2 that encodes the information. Where it is assumed that encoder 2 is a turbo product code (TPC) encoder, a parity bit is added to each row and to each column of table 1 to produce an even parity code (i.e., each column and each row contains an even number of 1's). Thus, the original information represented by a 3×2 table is formed into encoded information (ck) that is formed in a 4×3 table. The parity laden 4×3 table is represented as table 2 below.
TABLE 2Original Information Interleaved with Parity (ck)011110000101For simplicity, the example assumes that each column of table 2 corresponds to a single parity codeword. It may be, however, that a more complex interleaving may be utilized.
In this example the resulting codeword, ck=010111001001, is recorded by recording channel 3. When retrieved from recording channel 3, a signal (xk) provided from recording channel 3 may be corrupted by noise (nk) resulting in a corrupted signal (yk). The noise (nk) may be, for example, additive Gaussian noise. SOVA channel detector 4 receives the corrupted signal (yk) and produces hard decisions and corresponding soft reliability estimates. Decoder 5 receives the output of SOVA channel detector 4 and decodes the output to recover the original information using the interleaved parity information.
It has been recognized that various schemes such as the aforementioned scheme are often limited in their ability to detect and correct errors, or they are overly complex resulting in the wasteful use of circuitry and the corresponding waste of power. Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for error reduction.